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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30 termination resistors; 3-state
Rev. 03 -- 17 January 2005 Product data sheet
1. General description
The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at 3.3 V. The 74LVT162374 is designed with 30 series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
2. Features
s s s s s s s s s s s s s 16-bit edge-triggered flip-flop 3-state buffers Output capability: +12 mA and -12 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Outputs include series resistance of 30 making external resistors unnecessary Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection exceeds 500 mA per JESD78 ESD protection: x MIL STD 883 method 3015: exceeds 2000 V x Machine model: exceeds 200 V
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
3. Quick reference data
Table 1: Quick reference data Tamb = 25 C. Symbol Parameter Conditions CL = 50 pF; VCC = 3.3 V VI = 0 V or 3.0 V outputs disabled; VO = 0 V or 3.0 V outputs disabled; VCC = 3.6 V Min Typ 3.0 3 9 70 Max Unit ns pF pF A tPLH, tPHL propagation delay nCP to nQn CI CO ICC input capacitance output capacitance supply current
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74LVT162374DGG -40 C to +85 C 74LVT162374DL -40 C to +85 C TSSOP48 SSOP48 Description plastic thin shrink small outline package; 48 leads; body width 6.1 mm plastic shrink small outline package; 48 leads; body width 7.5 mm Version SOT362-1 SOT370-1 Type number
9397 750 14401
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Product data sheet
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Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
5. Functional diagram
47
46
44
43
41
40
38
37
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1 1CP 1OE
1 1OE 48 1CP 24 2OE 25 2CP 1D0 1D1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1EN C3 2EN C4 3D 1 2 3 5 6 8 9 11 12 4D 2 13 14 16 17 19 20 22 23
001aaa254
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1D2 1D3
2
3
5
6
8
9
11
12
1D4 1D5
36
35
33
32
30
29
27
26
1D6 1D7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2D0 2D1
25 24
2CP 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D2 2D3 2D4 2D5 2D6 2D7
13
14
16
17
19
20
22
23
001aac369
Fig 1. Logic symbol
Fig 2. IEC logic symbol
nD0 D
nD1 D
nD2 D
nD3 D
nD4 D
nD5 D
nD6 D
nD7 D
CP nCP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
001aac371
Fig 3. Logic diagram
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Product data sheet
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
VCC
27
output
27
001aac372
Fig 4. Output schematic (one output)
6. Pinning information
6.1 Pinning
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5
1 2 3 4 5 6 7 8 9
48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP
001aac370
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
162374
Fig 5. Pin configuration
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
6.2 Pin description
Table 3: Symbol 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 GND 1Q6 1Q7 2Q0 2Q1 GND 2Q2 2Q3 VCC 2Q4 2Q5 GND 2Q6 2Q7 2OE 2CP 2D7 2D6 GND 2D5 2D4 VCC 2D3 2D2 GND 2D1 2D0 1D7 1D6 GND
9397 750 14401
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Description output enable input (active LOW) data output data output ground (0 V) data output data output supply voltage data output data output ground (0 V) data output data output data output data output ground (0 V) data output data output supply voltage data output data output ground (0 V) data output data output output enable input (active LOW) clock pulse input (active rising edge) data input data input ground (0 V) data input data input supply voltage data input data input ground (0 V) data input data input data input data input ground (0 V)
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Product data sheet
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Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
Pin description Pin 40 41 42 43 44 45 46 47 48 Description data input data input supply voltage data input data input ground (0 V) data input data input clock pulse input (active rising edge)
Table 3: Symbol 1D5 1D4 VCC 1D3 1D2 GND 1D1 1D0 1CP
7. Functional description
7.1 Function table
Table 4: Function table [1] Input nOE Load and read register Hold Disable outputs L L L H H
[1]
Operating mode
Internal register Output nCP NC NC nDn l h X X nDn L H NC NC nDn nQ0 to nQ7 L H NC Z Z
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; NC = no change; X = don't care; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition.
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol VCC IIK VI IOK VO Parameter supply voltage input diode current input voltage output diode current output voltage VO < 0 V output in OFF-state or HIGH-state
[1]
Conditions VI < 0 V
[1]
Min -0.5 -50 -0.5 -50 -0.5
Max +4.6 +7.0 +7.0
Unit V mA V mA V
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Product data sheet
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
Table 5: Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol IO Tstg Tj
[1] [2]
Parameter output current storage temperature junction temperature
Conditions output in LOW-state output in HIGH-state
[2]
Min -65
Max 128 -64 +150 150
Unit mA mA C C
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal
9. Recommended operating conditions
Table 6: Symbol VCC VI VIH VIL IOH IOL t/V Tamb Recommended operating conditions Parameter supply voltage input diode voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input transition rise or fall outputs enabled rate ambient temperature Conditions Min 2.7 0 2.0 -40 Typ Max 3.6 5.5 0.8 -12 12 10 +85 Unit V V V V mA mA ns/V C
10. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIK VOH VOL VRST ILI Parameter C [1] VCC = 2.7 V; IIK = -18 mA VCC = 3.0 V; IOH = -12 mA VCC = 3.0 V; IOL = 12 mA
[2]
Conditions
Min 2.0 -
Typ -0.85 0.1
Max -1.2 0.8 0.55
Unit V V V V
Tamb = -40 C to +85
input clamp voltage HIGH-level output voltage LOW-level output voltage
power-up output low voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC input leakage current control pins I/O data pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V VCC = 0 V; VI or VO = 0 V to 4.5 V
-
0.1 0.4 0.1 -0.4 0.1
1 10 1 -5 100
A A A A A
IOFF
output off current
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Product data sheet
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol IHOLD Parameter bus hold current D inputs Conditions VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V VCC = 0 V to 3.6 V; VI = 3.6 V IEX external current into output output in HIGH-state when VO > VCC; measured at VO = 5.5 V and VCC = 3.0 V VCC 1.2 V; VO = 5.0 V to VCC; VI = GND or VCC; nOE and nOE = don't care VCC = 3.6 V; VO = 3.0 V; VI = VIH or VIL VCC = 3.6 V; VO = 0.5 V; VI = VIH or VIL VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled ICC additional supply current per VCC = 3 V to 3.6 V; one input at input pin VCC - 0.6 V; other inputs at VCC or GND input capacitance output capacitance VI = 0 V or 3.0 V outputs disabled; VO = 0 V or 3.0 V
[6] [7] [5] [4]
Min 75 -75 500 -
Typ 135 -135 50
Max 125
Unit A A A A
IPU, IPD
power-up or power-down 3-state output current 3-state output HIGH current 3-state output LOW current quiescent supply current
-
1
100
A
IOZH IOZL ICC
-
0.5 +0.5
5 -5
A A
-
0.07 4 0.07 0.1
0.12 6 0.12 0.2
mA mA mA mA
CI CO
[1] [2] [3] [4] [5] [6] [7]
-
3 9
-
pF pF
All typical values are at VCC = 3.3 V and Tamb = 25 C. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. Unused pins at VCC or GND. This is the bus-hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
Table 8: Dynamic characteristics GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; for test circuit see Figure 10. Symbol fmax tPLH Parameter C [1] VCC = 3.3 V 0.3 V; see Figure 6 see Figure 6 VCC = 3.3 V 0.3 V VCC = 2.7 V 1.5 3.0 5.3 6.2 ns ns 150 MHz maximum clock frequency propagation delay nCP to nQn Conditions Min Typ Max Unit Tamb = -40 C to +85
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
Table 8: Dynamic characteristics ...continued GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; for test circuit see Figure 10. Symbol tPHL Parameter propagation delay nCP to nQn Conditions see Figure 6 VCC = 3.3 V 0.3 V VCC = 2.7 V tPZH output enable time to HIGH-level see Figure 7 VCC = 3.3 V 0.3 V VCC = 2.7 V tPZL output enable time to LOW-level see Figure 8 VCC = 3.3 V 0.3 V VCC = 2.7 V tPHZ output disable time from HIGH-level see Figure 7 VCC = 3.3 V 0.3 V VCC = 2.7 V tPLZ output disable time from LOW-level see Figure 8 VCC = 3.3 V 0.3 V VCC = 2.7 V
[1] All typical values are at VCC = 3.3 V and Tamb = 25 C.
Min 1.5 1.5 1.5 1.5 1.5 -
Typ 3.0 3.5 3.2 3.5 3.2 -
Max 4.9 5.1 5.6 6.9 4.9 6.0 5.4 5.7 5.0 5.1
Unit ns ns ns ns ns ns ns ns ns ns
Table 9: Dynamic characteristics set-up requirements GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 . Symbol Parameter C [1] see Figure 9 VCC = 3.3 V 0.3 V VCC = 2.7 V th(H), th(L) hold time nDn to nCP see Figure 9 VCC = 3.3 V 0.3 V VCC = 2.7 V tW(H) nCP pulse width HIGH see Figure 6 VCC = 3.3 V 0.3 V VCC = 2.7 V tW(L) nCP pulse width LOW see Figure 6 VCC = 3.3 V 0.3 V VCC = 2.7 V
[1] All typical values are at VCC = 3.3 V and Tamb = 25 C.
Conditions
Min
Typ
Max
Unit
Tamb = -40 C to +85
tsu(H), tsu(L) set-up time nDn to nCP
2.0 2.0 0.8 0.1 1.5 1.5 3.0 3.0
0.7 0 0.6 1.6 -
-
ns ns ns ns ns ns ns ns
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Product data sheet
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
12. Waveforms
1/fmax 2.7 V nCP VM tW(H) tPHL nQn VM VM tW(L) VM 0V tPLH VOH VM VOL
001aac373
VM = 1.5 V; VI = GND to 3.0 V. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Propagation delay clock input to output, clock pulse width and maximum clock frequency
2.7 V nOE VM t PZH VM t PHZ VOH nQn VM VOH - 0.3 V 0V
001aac374
VM = 1.5 V; VI = GND to 3.0 V. VOH is typical voltage output drop that occur with the output load.
Fig 7. 3-state output enable time to HIGH-level and output disable time from HIGH-level
2.7 V nOE VM tPZL VM tPLZ 3.0 V nQn VM VOL + 0.3 V VOL
001aac375
VM = 1.5 V; VI = GND to 3.0 V. VOL is typical voltage output drop that occur with the output load.
Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level
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Product data sheet
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
2.7 V nDn VM VM VM VM 0V tsu(H) nCP th(H) VM tsu(L) th(L) 2.7 V VM 0V
001aac376
VM = 1.5 V; VI = GND to 3.0 V. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times
VI negative pulse 0V
tW 90 % VM 10 % tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) VM 90 %
VI positive pulse 0V 10 %
90 % VM tW
001aac221
VM 10 %
VM = 1.5 V.
a. Input pulse definition
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
mna616
Test data is given in Table 10. Definitions: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times.
b. Test circuit Fig 10. Load circuitry for switching times
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
Test data Repetition rate Input tW 10 MHz tr, tf Load CL RL 500 VEXT tPHZ, tPZH tPLZ, tPZL tPLH, tPHL GND 6V open
Table 10: Supply voltage 2.7 V
500 ns 2.5 ns 50 pF
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
13. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT362-1 (TSSOP48)
9397 750 14401 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 17 January 2005
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Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A X
c y HE vM A
Z 48 25
Q A2 A1 (A 3) Lp 1 bp 24 wM L detail X A
pin 1 index
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT370-1 (SSOP48)
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Product data sheet
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
14. Revision history
Table 11: Revision history Release date 20050117 Data sheet status Product data sheet Change notice Doc. number 9397 750 14401 Supersedes 74LVT162374_2 Document ID 74LVT162374_3 Modifications:
* * * *
The format of this data sheet is redesigned to comply with the current presentation and information standard of Philips Semiconductors. Section 2 "Features": Changed JEDEC Std 17 into JESD78 Table 1 "Quick reference data":Changed tPLH and tPHL propagation delays nCP to nQn to 3.0 ns Table 9 "Dynamic characteristics set-up requirements": Changed the minimum values of th(H) and th(L) hold time nDn to nCP to 0.8 ns Product specification Product specification 9397 750 14087 9397 750 06508 74LVT162374_1 -
74LVT162374_2 74LVT162374_1
20040922 19990923
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 16
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 17 January 2005 Document number: 9397 750 14401
Published in The Netherlands

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